VLSI (Very Large Scale Integrated) Design of a Sixteen Bit Pipelined Multiplier Using three Micron NMOS Technology.

Abstract

Abstract : The application of computer-aided design (CAD) tools in the full custom design and testing of a 16-bit pipelined two's complement multiplier in three micron NMOS is described. A comparison between the full custom carry-save addition (CSA) multiplier designed using CAD tools and a multiplier generated by the MacPitts silicon compiler is presented. Additional background material is also presented on the CSA multiplication algorithm used. Keywords: NMOS VLSI design; Pipelined multiplier; Two's complement multiplier; CAD tools; MacPitts silicon compiler; VLSI(Very Large Scale Integration); Integrated Circuits(Theses).